View CYDMX064A16-90BVXI_1648591.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

cydmx256a16, cydmx256b16 cydmx128a16, cydmx128b16 cydmx064a16, cydmx064b16 16 k/8 k/4 k 16 mobl ? adm asynchronous dual-port static ram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document #: 001-08090 rev. *g revised may 2, 2011 16 k/8 k/4 k 16 mobl ? adm asynchronous dual-port static ram features true dual-ported memory block that allow simultaneous independent access ? one port with dedicated time multiplexed address and data (adm) interface ? one port configurable to standard sram or time multiplexed address and data interface 16 k/8 k/4 k 16 memory configuration high speed access ? 65 ns or 90 ns adm interface ? 40 ns or 60 ns standard sram interface fully asynchronous operation port independent 1.8 v, 2.5 v, and 3.0 v ios ultra low operating power ? active: i cc = 15 ma (typical) at 90 ns ? active: i cc = 25 ma (typical) at 65 ns ? standby: i sb3 = 2 ? a (typical) port independent power down on-chip arbitration logic mailbox interrupt for port to port communication input read and output drive registers upper byte and lower byte control small package: 6 6 mm, 100-ball pb-free bga industrial temperature range notes 1. a13-a0 for cydmx256a16 and cydmx256b16; a12-a0 for cydmx128a16 and cydmx128b16; and a11-a0 for cydmx064a16 and cydmx064b16. 2. irr1 and irr2 not available for cydmx256a16 and cydmx256b16. block diagram mux'ed address / data i/o control address decode mux'ed address/ data i/o control i/ol15-i/ol8 i/ol7-i/ol0 address decode i/or15-i/or8 a13-a0 [note 1] control logic cs#l oe#l we#l busy#l int#l busy#r int#r cs#r oe#r we#r dual ported memory array 16k/8k/4k x 16 adv#l ub#l lb#l datal<15..0> datar<15..0> addrl<13..0> addrr<13..0> adv#r ub#r lb#r msel i/or7-i/or0 irr/odr sfen# irr1-irr0 [note 2] odr4-odr0 [+] feedback
cydmx256a16, cydmx256b16 cydmx128a16, cydmx128b16 cydmx064a16, cydmx064b16 document #: 001-08090 rev. *g page 2 of 25 contents pin configurations ........................................................... 3 pin definitions .................................................................. 4 functional description ..................................................... 4 power supply .............................................................. 4 adm interface read or write operation ..................... 4 standard sram interface read or write operation ... 5 byte select operation ................................................. 5 chip select operation ................................................. 5 output enable operation ........ .............. .............. ......... 5 mailbox interrupts ........................................................ 5 arbitration logic .... .............. .............. .............. ............ 5 input read register .................................................... 5 output drive register .................................................. 5 architecture ...................................................................... 6 maximum ratings ............................................................. 8 operating range ............................................................... 8 electrical characteristics for vcc = 1.8 v ...................... 8 electrical characteristics for vcc = 2.5 v .................... 10 electrical characteristics for 3.0 v ............................... 11 capacitance .................................................................... 11 switching characteristics for vcc = 1.8 v ................... 12 switching waveforms .................................................... 15 ordering information ...................................................... 21 ordering code definitions ..... .................................... 21 package diagram ............................................................ 22 acronyms ........................................................................ 23 document conventions ................................................. 23 units of measure ....................................................... 23 document history page ................................................. 24 sales, solutions, and legal information ...................... 25 worldwide sales and design s upport ......... .............. 25 products .................................................................... 25 psoc solutions ......................................................... 25 [+] feedback
cydmx256a16, cydmx256b16 cydmx128a16, cydmx128b16 cydmx064a16, cydmx064b16 document #: 001-08090 rev. *g page 3 of 25 notes 3. this pin is a13 for cydmx256a16 and cydmx256b16. 4. this pin is dnu for cydmx064a16 and cydmx064b16. 5. this pin is dnu for cydmx256a16 and cydmx256b16. 6. dnu pins are ?do not use? pins. no trace or power component can be connected to these pins. pin configurations figure 1. 100-ball 0.5 mm pitch bga (top view) . 12345678910 a a5 a8 a11 ub#r vss adv#r i/or15 i/or12 i/or10 vss a b a3 a4 a7 a9 ce#r we#r oe#r vddior i/or9 i/or6 b c a0 a1 a2 a6 lb#r irr1 [3] i/or14 i/or11 i/or7 vss c d odr4 odr2 busy#r int#r a10 a12 [4] i/or13 i/or8 i/or5 i/o2r d e vss dnu odr3 int#l vss vss i/or4 vddior i/or1 vss e f sfen# odr1 busy#l dnu vcc vss i/or3 i/or0 i/ol15 vddiol f g odr0 dnu dnu dnu oe#l i/ol3 i/ol11 i/ol12 i/ol14 i/ol13 g h dnu dnu dnu lb#l ce#l i/ol1 vddiol msel dnu i/ol10 h j dnu dnu dnu irr0 [5] vcc vss i/ol4 i/ol6 i/ol8 i/ol9 j k dnu dnu dnu ub#l adv#l we#l i/ol0 i/ol2 i/ol5 i/ol7 k 12345678910 [+] feedback
cydmx256a16, cydmx256b16 cydmx128a16, cydmx128b16 cydmx064a16, cydmx064b16 document #: 001-08090 rev. *g page 4 of 25 functional description the cydmx256a16, cydmx128a16, cydmx064a16, cydmx256b16, cydmx128b16, and cydmx064b16 are low power cmos 16k/8k/4k 16 dual-port static rams. the two ports are: one dedicated time multiplexed address and data (adm) interface and one configurable standard sram or adm interface. the two ports permit independent, asynchronous read and write access to any memory locations. each port has independent control pins: chip select (cs#), write enable (we#), and output enable (oe#). two output flags are provided on each port (busy# and int#). busy# flag is triggered when the port is trying to access th e same memory lo cation currently being accessed by the other port. the interrupt flag (int#) permits communication between ports or systems by means of a mailbox. power down feature is controlled independently on each port by a chip select (cs#) pin. the cydmx256a16, cydmx128a16, cydmx064a16, cydmx256b16, cydmx128b16, and cydmx064b16 are available in 100-ball 0.5-mm pitch ball grid array (bga) packages. application areas include interprocessor and multiprocessor designs, communications status buffering, and dual-port video and graphics memory. power supply the core voltage (v cc ) can be 1.8 v, 2.5 v, or 3.0 v, as long as it is lower than or equal to the io voltage. each port operates on independent io voltages. this is determined by what is connected to the v ddiol and v ddior pins. the supported io standards are 1.8 v and 2.5 v lvcmos and 3.0 v lvttl. adm interface read or write operation this description is applicable to both the left adm port and right port configured as an adm port. three control signals, adv#, we#, and cs# are used to perform the read and write operations. address signals are first applied to the io bus along with cs# low. the addresses are loaded from the io bus in response to the rising edge of the address latch enable (adv#) signal. it is necessary to meet the setup (t avds ) and hold (t avdh ) times given in the ac specifications with valid address information to properly latch the addresses. after the address signals are latched in, a read operation is issued when we# stays high. the io bus becomes high z when the address signals meet t avdh . the read data is driven on the io bus t oe after the oe# is asserted low, and held until t hzoe or t hzcs after the rising edge of oe# or cs#, whichever comes first. a write operation is issued when we# is asserted low. the write data is applied to the io bus right after address meets the hold time (t avdh ). and write data is written with the rising edge of either we# or cs#, whichever comes first, and meets data setup (t sd ) and hold (t hd ) times. pin definitions left port right port description cs#l cs#r chip select we#l we#r read/write enable oe#l oe#r output enable a0?a13 address (a0?a11 for 4k device; a0?a12 for 8k device; a0?a13 for 16k device) msel right port interface mode select (0 : standard sram; 1: address/data mux) iol0?iol15 ior0?ior15 address/data bus input/output adv#l adv#r address latch enable; adv#r on ly use when r-port is in adm mode ub#l ub#r upper byte select (io8?io15) lb#l lb#r lower byte select (io0?io7) int#l int#r interrupt flag busy#l busy#r busy flag sfen# special function enable signal irr0-irr1 input signals for input read r egisters for cydmx128a16, cydmx128b16, cydmx064a16 and cydmx064b16; irr0 is dnu and irr1 is a13 for cydmx256a16 and cydmx256b16. odr0-odr4 output signals for output drive r egisters; these are open drained outputs. vcc core power supply gnd ground vddiol left port io power supply vddior right port io power supply dnu no connect; do not connect trace or power component to these pins. [+] feedback
cydmx256a16, cydmx256b16 cydmx128a16, cydmx128b16 cydmx064a16, cydmx064b16 document #: 001-08090 rev. *g page 5 of 25 standard sram interface read or write operation this description is applicable to the right access port configured as standard sram port. read and write operations with standard sram interface configur ation is the same as the adm port except addresses are pres ented on the a bus. operation is controlled by cs#, oe#, and we#. a read operation is issued when we# is asserted high. a wr ite operation is issued when we# is asserted low. the io bus is the destination for read data and the source for write data when the read operation is issued. however, write data must be driven to io when the write operation is issued. byte select operation the fundamental word size is 16 bits. each word is broken up into two 8-bit bytes. each port has two active low byte enables: ub# and lb#. activating or deactivating the byte enables alters the result of read and write opera tions to the port. during a write, byte enable asserted high inhibits the corresponding byte to be updated in the addressed memory location. during a read, both byte enables are inputs to the asynchronous output enable control logic. when a byte enable is asserted high, the corresponding data byte is tri- stated. subsequently, when the byte enable is asserted low, the corresponding data byte is driven with the read data. chip select operation each port has one active low chip select signal, cs#. cs# must be asserted low for the port to be considered active. to issue a valid read or write operation, the chip select input must be asserted low throughout the read or write cycle. when cs# is deasserted high during a write, if t wrl , t sd, and t hd are not met, the contents of the addressed location is not altered. an automatic power dow n feature controlled by deactivating the chip select (cs# high) permits the on-chip circuitry of each port to enter a very low standby power mode. output enable operation each port has one output enable signal, oe#. when oe# is asserted high, io bus is tri-stated after t hzoe . when oe# is asserted low, control of the io bus is assumed by the asynchronous output enable logic (the logic is controlled by inputs we#, cs#, ub#, and lb#). mailbox interrupts the upper two memory locations are used for message passing. the highest memory location (0xfff for cydmx064a16 and cydmx064b16, 0x1fff for cydmx128a16 and cydmx128b16, and 0x3fff for cydmx256a16 and cydmx256b16) is the mailbox for the right port. the second highest memory location (0xffe for cydmx064a16 and cydmx064b16, 0x1ffe for cydmx128a16 and cydmx128b16, and 0x3ffe for cydmx256a16 and cydmx256b16) is the mailbox for the left port. when one port writes to the opposite port?s mailbox, an interrupt signal is generated to the opposite port. the interrupt resets when the owner reads the contents of its own mailbox. the message written to the mailbox is user defined. each port reads the other port?s mailbox without resetting the interrupt. the active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. also, an active busy to a port prevents that port from reading its own mailbox and resetting the interrupt to it. on power up, both interrupts are se t by default. an initialization program must be run to reset the interrupts. if an application does not require message passing, do not connect the interrupt pin to the processor?s interrupt request input pin. arbitration logic the cydmx256a16, cydmx128a16, cydmx064a16, cydmx256b16, cydmx128b16, and cydmx064b16 provide on-chip arbitration to resolve simultaneous memory location access (collision). if both ports? cs# signals are asserted and an address match occurs within each other, the busy logic deter- mines which port has access. if t ps is violated, one of the two ports gains permission to the location, but it is not predictable which port gets the permission. busy# is asserted t bla after an address match or t blc after cs# is taken low. input read register the input read register (irr) feature is available only for cydmx128a16, cydmx128b 16, cydmx064a16, and cydmx064b16 devices. when sfen# = v il , the irr captures the status of two external devices connected to the input read pins (irr0 and irr1) to address location 0x0000. address 0x0000 is not available for standard memory accesses when sfen# = v il. when sfen# = v ih , address 0x0000 is available for normal memory accesses. eith er port accesses the contents of irr with normal read operation from address 0x0000. during reads from the irr, io<1:0> are valid bits and io<15:2> are don?t care. the irr inputs are 1. 8 v and 2.5 v lvcmos or 3.0 v lvttl, depending on the core voltage supply (v cc ). output drive register the output drive register (odr) determines the state of up to five external binary state devices by providing a path to v ss for the external circuit. these outputs are open drain. the five external devices operates at different voltages (1.5 v ? v ddio ? 3.5 v) but the combined current cannot exceed 40 ma (8 ma maximum for each external device). the status of the odr bits are set using standard write accesses from either port to address 0x0001 with a ?1? corresponding to on and ?0? corresponding to off. the status of the odr bits are read with a normal read access to address 0x0001. when sfen# = v il , the odr is active and address 0x0001 is not available for memory accesses. when sfen# = v ih , the odr is inactive and address 0x0001 is used for standard accesses. during reads and writes to odr, io<4:0> are valid and io<15:5> are don?t care. [+] feedback
cydmx256a16, cydmx256b16 cydmx128a16, cydmx128b16 cydmx064a16, cydmx064b16 document #: 001-08090 rev. *g page 6 of 25 architecture the cydmx256a16, cydmx128a16, cydmx064a16, cydmx256b16, cydmx128b16, and cydmx064b16 consist of an array of 16k, 8k, and 4k words of 16 dual-ported sram cells, io, address lines, and control signals (cs#, adv#, oe#, and we#). between the two access ports, one is a dedicated time multiplexed address and data interface; the other is a pin selectable port to either standard sram or time multiplexed address and data interface. independent control signals for each port permit simultaneous access to any location in memory. to handle the situation of writing and reading to the same location, a busy# pin is provided on each port. for port to port communication, an interrupt (int#) pin is also available on each port. table 1. adm interface read/write with byte select operations adv# cs# we# oe# ub# lb# io0 - io15 mode x h x x x x high z deselected or power down x x x h x x high z output disable xxxxhhhigh z upper and lower byte deselected pulse l h l l l data out (io0-io15) read upper and lower bytes pulse l h l h l data out (io0-io7) high z (io8-io15) read lower byte only pulse l h l l h high z (io0-io7) data out (io8-io15) read upper byte only pulse l l x l l data in (io0-io15) write upper and lower bytes pulse l l x h l data in (io0-io7) high z (io8-io15) write lower byte only pulse l l x l h high z (io0-io7) data in (io8-io15) write upper byte only table 2. standard sram interface read/write with byte select operations cs# we# oe# ub# lb# io0-io15 mode h x x x x high z deselected or power down x x h x x high z output disable x x x h h high z upper and lower byte deselected l h l l l data out (io0-io15) read upper and lower bytes l h l h l data out (io0-io7) high z (io8-io15) read lower byte only l h l l h high z (io0-io7) data out (io8-io15) read upper byte only l l x l l data in (io0-io15) write upper and lower bytes l l x h l data in (io0-io7) high z (io8-io15) write lower byte only l l x l h high z (io0-io7) data in (io8-io15) write upper byte only [+] feedback
cydmx256a16, cydmx256b16 cydmx128a16, cydmx128b16 cydmx064a16, cydmx064b16 document #: 001-08090 rev. *g page 7 of 25 table 3. interrupt operation example (assumes busy#l = busy#r = high) function left port right port we#l cs#l oe#l addressl int#l we#r cs#r oe#r addressr int#r set right int#r flag l l x 0x3fff [7] xxxx x l reset right int#r flag x x x x x x l l 0x3fff [7] h set left int#l flag x x x x l l l x 0x3ffe [8] x reset left int#l flag x l l 0x3ffe [8] hxxx x x table 4. arbitration winning port cs#l cs#r address match left/right port busy#l busy#r function x x no match h h normal hx match hh normal xh match hh normal l l match see note [9] see note [9] write inhibit [10] table 5. input read register operation [11] sfen# cs# we# oe# ub# lb# addr io 0 ? io 1 io 2 ? io 15 mode hlhlllx0000-maxvalid [12] valid [12] standard memory access l l h l x l x0000 valid [13] x irr read table 6. output drive register [15] sfen# cs# we# oe# ub# lb# addr io 0 ? io 4 io 5 ? io 15 mode hlhx [16] l [12] l [12] x0000-max valid [12] valid [12] standard memory access lllxxlx0001valid [13] x odr write [17] llhlxlx0001valid [13] x odr read notes 7. 0x3fff for cydmx256a16 and cydmx256b16, 0x1fff for cydmx128a16 and cydmx128b16, 0xfff for cydmx064a16 and cydmx064b16. 8. 0x3ffe for cydmx256a16 and cydmx256b16, 0x1ffe for cydmx128a16 and cydmx128b16, 0xffe for cydmx064a16 and cydmx064b16. 9. if it meets tps, "l" if the cs# and address of the opposite port become stable before the current port; "h" if the cs# and ad dress of the opposite port become stable after the current port. if tps is not met, either busy#l or busy#r results ?l?. busy#l and busy#r cannot be ?l? simultan eously. 10. write operations to the left port are internally ignored wh en busy#l is driving low regardless of actual logic level on the pin; write operations to the right port are internally ignored when busy#r is driving lo w regardless of actual logic level on the pin. 11. sfen# = v il for irr reads. 12. ub# or lb# = v il . if lb# = v il , then io<7:0> are valid. if ub# = v il then io<15:8> are valid. 13. lb# must be active (lb# = v il ) for these bits to be valid. 14. sfen# active when either cs#l = v il or cs#r = v il . it is inactive when cs#l = cs#r = v ih . 15. sfen# = v il for odr reads and writes. 16. output enable must be low (oe# = v il ) during reads for valid data to be output. 17. during odr writes data is also written to the memory. [+] feedback
cydmx256a16, cydmx256b16 cydmx128a16, cydmx128b16 cydmx064a16, cydmx064b16 document #: 001-08090 rev. *g page 8 of 25 maximum ratings exceeding maximum ratings [18] may shorten the useful life of the device. user guidelines are not tested. storage temperature ................. ............... ?65 c to +150 c ambient temperature with power applied ............ ............... ............... ?55 c to +125 c supply voltage to ground potentia l..............?0.5 v to +3.3 v dc voltage applied to outputs in high z state ....................... ?0.5 v to v cc + 0.5 v dc input voltage [19] ............................. ?0.5 v to v cc + 0.5 v output current into outputs (low)............................. 90 ma static discharge voltage......................................... > 2000 v latch up current.................................................... > 200 ma operating range range ambient temperature v cc industrial ?40 c to +85 c 1.8 v 100 mv 2.5 v 100 mv 3.0 v 300 mv electrical characteristics for v cc = 1.8 v over the operating range parameter description cydmx256a16 cydmx128a16 cydmx256b16 cydmx128b16 cydmx064b16 cydmx256a16 cydmx128a16 cydmx064a16 unit ?65 ?65 ?90 p1 io voltage p2 io voltage min typ max min typ max min typ max v oh output high voltage (i oh = ?100 ? a) 1.8 v (any port) v ddio ? 0.2 ??v ddio ? 0.2 ??v ddio ? 0.2 ??v output high voltage (i oh = ?2 ma) 2.5 v (any port) 2.0 ? ? 2.0 ? ? 2.0 ? ? v output high voltage (i oh = ?2 ma) 3.0 v (any port) 2.1 ? ? 2.1 ? ? 2.1 ? ? v v ol output low voltage (i ol = 100 ? a ? 1.8 v (any port) ? ? 0.2 ? ? 0.2 ? ? 0.2 v output high voltage (i oh = 2 ma) 2.5 v (any port) ? ? 0.4 ? ? 0.4 ? ? 0.4 v output high voltage (i oh = 2 ma) 3.0 v (any port) ? ? 0.4 ? ? 0.4 ? ? 0.4 v v ol odr odr output low voltage (i ol = 8 ma ? 1.8 v (any port) ? ? 0.2 ? ? 0.2 ? ? 0.2 v 2.5 v (any port) ? ? 0.2 ? ? 0.2 ? ? 0.2 v 3.0 v (any port) ? ? 0.2 ? ? 0.2 ? ? 0.2 v v ih input high voltage 1.8 v (any port) 1.2 ? v ddio + 0.2 1.2 ? v ddio + 0.2 1.2 ? v ddio + 0.2 v 2.5 v (any port) 1.7 ? v ddio + 0.3 1.7 ? v ddio + 0.3 1.7 ? v ddio + 0.3 v 3.0 v (any port) 2.0 ? v ddio + 0.2 2.0 ? v ddio + 0.2 2.0 ? v ddio + 0.2 v v il input low voltage 1.8 v (any port) ?0.2 ? 0.4 ?0.2 ? 0.4 ?0.2 ? 0.4 v 2.5 v (any port) ?0.3 ? 0.6 ?0.3 ? 0.6 ?0.3 ? 0.6 v 3.0 v (any port) ?0.2 ? 0.7 ?0.2 ? 0.7 ?0.2 ? 0.7 v i oz output leakage current 1.8 v 1.8 v ?1 ? 1 ?1 ? 1 ?1 ? 1 ? a 2.5 v 2.5 v ?1 ? 1 ?1 ? 1 ?1 ? 1 ? a 3.0 v 3.0 v ?1 ? 1 ?1 ? 1 ?1 ? 1 ? a i cex odr odr output leakage current. v out = v ddio 1.8 v 1.8 v ?1 ? 1 ?1 ? 1 ?1 ? 1 ? a 2.5 v 2.5 v ?1 ? 1 ?1 ? 1 ?1 ? 1 ? a 3.0 v 3.0 v ?1 ? 1 ?1 ? 1 ?1 ? 1 ? a notes 18. the voltage on any input or io pin cannot exceed the power pin during power up. 19. pulse width < 20 ns. [+] feedback
cydmx256a16, cydmx256b16 cydmx128a16, cydmx128b16 cydmx064a16, cydmx064b16 document #: 001-08090 rev. *g page 9 of 25 i ix input leakage current 1.8 v 1.8 v ?1 ? 1 ?1 ? 1 ?1 ? 1 ? a 2.5 v 2.5 v ?1 ? 1 ?1 ? 1 ?1 ? 1 ? a 3.0 v 3.0 v ?1 ? 1 ?1 ? 1 ?1 ? 1 ? a i cc operating current (v cc = max, i out = 0 ma) outputs disabled ind. 1.8 v 1.8 v ? 25 40 ? 25 40 ? 15 25 ma i sb1 standby current (both ports ttl level) ce#l and ce#r ? v cc ? 0.2, f = f max ind. 1.8 v 1.8 v ? 2 6 ? 2 6 ? 2 6 ? a i sb2 standby current (one port ttl level) ce#l or ce#r ? v ih , f = f max ind. 1.8 v 1.8 v ? 8.5 18 ? 8.5 18 ? 8.5 14 ma i sb3 standby current (both ports cmos level) ce#l and ce#r ? v cc ?? 0.2 v, f = 0 ind. 1.8 v 1.8 v ? 2 6 ? 2 6 ? 2 6 ? a i sb4 standby current (one port cmos level) ce#l or ce#r ? v ih , f = f max [20] ind. 1.8 v 1.8 v ? 8.5 18 ? 8.5 18 ? 8.5 14 ma electrical characteristics for v cc = 1.8 v (continued) over the operating range (continued) parameter description cydmx256a16 cydmx128a16 cydmx256b16 cydmx128b16 cydmx064b16 cydmx256a16 cydmx128a16 cydmx064a16 unit ?65 ?65 ?90 p1 io voltage p2 io voltage min typ max min typ max min typ max note 20. f max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control lines change. this applies only to inputs at cmos level standby i sb3 . [+] feedback
cydmx256a16, cydmx256b16 cydmx128a16, cydmx128b16 cydmx064a16, cydmx064b16 document #: 001-08090 rev. *g page 10 of 25 electrical characteristics for v cc = 2.5 v over the operating range parameter description cydmx256a16 cydmx128a16 cydmx256b16 cydmx128b16 cydmx064b16 cydmx256a16 cydmx128a16 cydmx064a16 unit ?65 ?65 ?90 p1 io voltage p2 io voltage min typ max min typ max min typ max v oh output high voltage (i oh = ?2 ma) 2.5 v (any port) 2.0 ? ? 2.0 ? ? 2.0 ? ? v 3.0 v (any port) 2.1 ? ? 2.1 ? ? 2.1 ? ? v v ol output low voltage (i ol = 2 ma ? 2.5 v (any port) ? ? 0.4 ? ? 0.4 ? ? 0.4 v 3.0 v (any port) ? ? 0.4 ? ? 0.4 ? ? 0.4 v v ol odr odr output low voltage (i ol = 8 ma ? 2.5 v (any port) ? ? 0.2 ? ? 0.2 ? ? 0.2 v 3.0 v (any port) ? ? 0.2 ? ? 0.2 ? ? 0.2 v v ih input high voltage 2.5 v (any port) 1.7 ? v ddio + 0.3 1.7 ? v ddio + 0.3 1.7 ? v ddio + 0.3 v 3.0 v (any port) 2.0 ? v ddio + 0.2 2.0 ? v ddio + 0.2 2.0 ? v ddio + 0.2 v v il input low voltage 2.5 v (any port) ?0.3 ? 0.6 ?0.3 ? 0.6 ?0.3 ? 0.6 v 3.0 v (any port) ?0.2 ? 0.7 ?0.2 ? 0.7 ?0.2 ? 0.7 v i oz output leakage current 2.5 v 2.5 v ?1 ? 1 ?1 ? 1 ?1 ? 1 ? a 3.0 v 3.0 v ?1 ? 1 ?1 ? 1 ?1 ? 1 ? a i cex odr odr output leakage current. v out = v cc 2.5 v 2.5 v ?1 ? 1 ?1 ? 1 ?1 ? 1 ? a 3.0 v 3.0 v ?1 ? 1 ?1 ? 1 ?1 ? 1 ? a i ix input leakage current 2.5 v 2.5 v ?1 ? 1 ?1 ? 1 ?1 ? 1 ? a 3.0 v 3.0 v ?1 ? 1 ?1 ? 1 ?1 ? 1 ? a i cc operating current (v cc = max, i out = 0 ma) outputs disabled ind. 2.5 v 2.5 v ? 39 55 ? 39 55 ? 28 40 ma i sb1 standby current (both ports ttl level) ce#l and ce#r ? v cc ? 0.2, f = f max ind.2.5 v2.5 v?68?68?68 ? a i sb2 standby current (one port ttl level) ce#l or ce#r ? v ih , f = f max ind. 2.5 v 2.5 v ? 21 30 ? 21 30 ? 18 25 ma i sb3 standby current (both ports cmos level) ce#l and ce#r ? v cc ?? 0.2 v, f = 0 ind.2.5 v2.5 v?46?46?46 ? a i sb4 standby current (one port cmos level) ce#l or ce#r ? v ih , f = f max [21] ind. 2.5 v 2.5 v ? 21 30 ? 21 30 ? 18 25 ma note 21. f max = 1/t rc = all inputs cycling at f = 1/t rc (except output enable). f = 0 means no address or control lines change. this applies only to inputs at cmos level standby i sb3 . [+] feedback
cydmx256a16, cydmx256b16 cydmx128a16, cydmx128b16 cydmx064a16, cydmx064b16 document #: 001-08090 rev. *g page 11 of 25 electrical characteristics for 3.0 v over the operating range parameter description cydmx256a16 cydmx128a16 cydmx256b16 cydmx128b16 cydmx064b16 cydmx256a16 cydmx128a16 cydmx064a16 unit ?65 ?65 ?90 p1 io voltage p2 io voltage min typ max min typ max min typ max v oh output high voltage (i oh = ?2 ma) 3.0 v (any port) 2.1 ? ? 2.1 ? ? 2.1 ? ? v v ol output low voltage (i ol = 2 ma ? 3.0 v (any port) ? ? 0.4 ? ? 0.4 ? ? 0.4 v v ol odr odr output low voltage (i ol = 8 ma ? 3.0 v (any port) ? ? 0.2 ? ? 0.2 ? ? 0.2 v v ih input high voltage 3.0 v (any port) 2.0 ? v ddio + 0.2 2.0 ? v ddio + 0.2 2.0 ? v ddio + 0.2 v v il input low voltage 3.0 v (any port) ?0.2 ? 0.7 ?0.2 ? 0.7 ?0.2 ? 0.7 v i oz output leakage current 3.0 v 3.0 v ?1 ? 1 ?1 ? 1 ?1 ? 1 ? a i cex odr odr output leakage current. v out = v cc 3.0 v 3.0 v ?1 ? 1 ?1 ? 1 ?1 ? 1 ? a i ix input leakage current 3.0 v 3.0 v ?1 ? 1 ?1 ? 1 ?1 ? 1 ? a i cc operating current (v cc = max, i out = 0 ma) outputs disabled ind. 3.0 v 3.0 v ? 49 70 ? 49 70 ? 42 60 ma i sb1 standby current (both ports ttl level) ce#l and ce#r ? v cc ? 0.2, f = f max ind. 3.0 v 3.0 v 7 10 7 10 7 10 ? a i sb2 ind. 3.0 v 3.0 v 28 40 28 40 25 35 ma i sb3 standby current (one port ttl level) ce#l or ce#r ? v ih , f = f max ind. 3.0 v 3.0 v 6 8 6 8 6 8 ? a i sb4 ind. 3.0 v 3.0 v 28 40 28 40 25 35 ma capacitance [22] parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 3.0 v 9 pf c out output capacitance 10 pf note 22. tested initially and after any design or proces s changes that may affect these parameters. [+] feedback
cydmx256a16, cydmx256b16 cydmx128a16, cydmx128b16 cydmx064a16, cydmx064b16 document #: 001-08090 rev. *g page 12 of 25 figure 2. ac test loads and waveforms 1.8 v gnd 90% 90% 10% 10% all input pulses (a) normal load r1 3.0 v/2.5 v/1.8 v output r2 c = 30 pf v th = 0.8 v output (b) thvenin equivalent (load 1) (c) three-state delay (load 2) r1 r2 3.0 v/2.5 v/1.8 v output r th = 6 k ? ?? 3 ns ?? 3 ns including scope and jig) (used for t lz , t hz , t hzwe , and t lzwe 3.0 v/2.5 v 1.8 v r1 1022 ? 13500 ? r2 792 ? 10800 ? c = 30 pf c = 5 pf switching characteristics for v cc = 1.8 v over the operating range [23] parameter description cydmx256a16 cydmx128a16 cydmx256b16 cydmx128b16 cydmx064b16 cydmx256a16 cydmx128a16 cydmx064a16 unit ?65 ?65 ?90 min max min max min max ad mux port read cycle [24] trc read cycle time 65 ? 65 ? 90 ? ns tacc1 random access adv# low to data valid ? 65 ? 65 ? 90 ns tacc2 random access address to data valid ? 65 ? 65 ? 90 ns tacc3 random access cs# to data valid ? 65 ? 65 ? 90 ns tavda random access adv# high to data valid ? 35 ? 35 ? 50 ns tavd adv# low pulse 15 ? 15 ? 20 ? ns tavds address setup-up to adv# rising edge 15 ? 15 ? 20 ? ns tavdh address hold from adv# rising edge 3 ? 3 ? 5 ? ns tcss cs# set-up to adv# rising edge 7 ? 7 ? 10 ? ns toe oe# low to data valid ? 35 ? 35 ? 50 ns tlzoe [25] oe# low to io low z 3 ? 3 ? 5 ? ns thzoe oe# high to io high z ? 15 ? 15 ? 25 ns thzcs cs# high to io high z ? 15 ? 15 ? 25 ns tdbe ub#/lb# low to io valid ? 35 ? 35 ? 50 ns tlzbe ub#/lb# low to io low z 3 ? 3 ? 5 ? ns thzbe ub#/lb# high to io high z ? 15 ? 15 ? 25 ns tavoe adv# high to oe# low 0 ? 0 ? 0 ? ns notes 23. all timing parameters are measured with load 2 specified in figure 2 . 24. ad mux port timing applies to left ad mux port and right port configured to ad mux port. 25. this parameter is guaranteed by not tested. [+] feedback
cydmx256a16, cydmx256b16 cydmx128a16, cydmx128b16 cydmx064a16, cydmx064b16 document #: 001-08090 rev. *g page 13 of 25 ad mux port write cycle [26] twc write cycle time 65 ? 65 ? 90 ? ns tscs cs# low to write end 65 ? 65 ? 90 ? ns tavd adv# low pulse 15 ? 15 ? 20 ? ns tavds address set-up to adv# rising edge 15 ? 15 ? 20 ? ns tavdh address hold from adv# rising edge 3 ? 3 ? 5 ? ns tcss cs# set-up to adv# rising edge 7 ? 7 ? 10 ? ns twrl we# pulse width 28 ? 28 ? 45 ? ns tbw ub#/lb# low to write end 28 ? 28 ? 45 ? ns tsd data set-up to write end 20 ? 20 ? 30 ? ns thd data hold from write end 0 ? 0 ? 0 ? ns tlzwe we# high to io low z 0 ? 0 ? 0 ? ns tavwe adv# high to we# low 0 ? 0 ? 0 ? ns standard port read cycle [27] trc read cycle time 40 ? 60 ? 60 ? ns taa address to data valid ? 40 ? 60 ? 60 ns toha output hold from address change 5 ? 5 ? 5 ? ns tacs cs# to data valid ? 40 ? 60 ? 60 ns tdoe oe# low to data valid ? 25 ? 35 ? 35 ns tlzoe [28] oe# low to data low z 5 ? 5 ? 5 ? ns thzoe oe# high to data high z ? 10 ? 30 ? 30 ns tlzcs cs# low to data low z 5 ? 5 ? 5 ? ns thzcs cs# high to data high z ? 10 ? 30 ? 30 ns tlzbe ub#/lb# low to data low z 5 ? 5 ? 5 ? ns thzbe ub#/lb# high to data high z ? 10 ? 30 ? 30 ns tabe ub#/lb# access time ? 40 ? 60 ? 60 ns standard sram port write cycle twc write cycle time 40 ? 60 ? 60 ? ns tscs cs# low to write end 30 ? 50 ? 50 ? ns taw address valid to write end 30 ? 50 ? 50 ? ns tha address hold from write end 0 ? 0 ? 0 ? ns tsa address set-up to write start 0 ? 0 ? 0 ? ns switching characteristics for v cc = 1.8 v (continued) over the operating range [23] (continued) parameter description cydmx256a16 cydmx128a16 cydmx256b16 cydmx128b16 cydmx064b16 cydmx256a16 cydmx128a16 cydmx064a16 unit ?65 ?65 ?90 min max min max min max notes 26. ad mux port timing applies to left ad mux port and right port configured to ad mux port. 27. standard sram port timing applies to right port configured to standard sram port. 28. this parameter is guaranteed by not tested. [+] feedback
cydmx256a16, cydmx256b16 cydmx128a16, cydmx128b16 cydmx064a16, cydmx064b16 document #: 001-08090 rev. *g page 14 of 25 twrl write pulse width 25 ? 45 ? 45 ? ns tsd data set-up to write end 20 ? 30 ? 30 ? ns thd data hold from write end 0 ? 0 ? 0 ? ns thzwe we# low to data high z ? 15 ? 25 ? 25 ns tlzwe we# high to data low z 0 ? 0 ? 0 ? ns arbitration timing tbla busy# low from address match ? 30 ? 50 ? 50 ns tbha busy# high from address mismatch ? 30 ? 50 ? 50 ns tblc busy# low from cs# low ? 30 ? 50 ? 50 ns tbhc busy# high from cs# high ? 30 ? 50 ? 50 ns tps [29] port set-up fro priority 5 ? 5 ? 5 ? ns tbdd busy# high to data valid ? 30 ? 50 ? 50 ns twdd write pulse to data delay ? 55 ? 85 ? 85 ns tddd write data valid to read data valid ? 45 ? 70 ? 70 ns interrupt timing tins int# set time ? 35 ? 55 ? 55 ns tinr int# reset time ? 35 ? 55 ? 55 ns switching characteristics for v cc = 1.8 v (continued) over the operating range [23] (continued) parameter description cydmx256a16 cydmx128a16 cydmx256b16 cydmx128b16 cydmx064b16 cydmx256a16 cydmx128a16 cydmx064a16 unit ?65 ?65 ?90 min max min max min max note 29. add 2 ns to this parameter if vcc and vddior are < 1.8 v, and vddiol is > 2.5 v at temperature < 0 c. [+] feedback
cydmx256a16, cydmx256b16 cydmx128a16, cydmx128b16 cydmx064a16, cydmx064b16 document #: 001-08090 rev. *g page 15 of 25 switching waveforms figure 3. adm port read cycle (either port access, we# high) figure 4. adm port write cycle (eithe r port access, we# controlled, oe# high) valid address i/o[15:0] adv# oe# we# cs# valid data t a v d tavds tavdh tcss tavoe tacc3 tacc1 tacc2 thzcs thzoe tavda toe ub#, lb# tlzbe tdbe thzbe addr1<15..0> i/o[15:0] adv# oe# we# cs# wdata1<15..0> tavwe twrl tsd thd t a v d tavds tavdh tcss tscs ub#, lb# tbw [+] feedback
cydmx256a16, cydmx256b16 cydmx128a16, cydmx128b16 cydmx064a16, cydmx064b16 document #: 001-08090 rev. *g page 16 of 25 figure 5. adm port write cycle (eithe r port access, cs# controlled, oe# high) figure 6. standard port read cycle (right port access, we# high) addr1<15..0> i/o[15:0] adv# oe# we# cs# wdata1<15..0> tavwe t w r l t s d t h d t a v d tavds tavdh tcss t s c s ub#, lb# t b w valid address address oe# we# cs# trc thzcs thzoe ub#, lb# thzbe data out valid data toha taa tacs tdoe tlzoe tlzcs tabe tlzbe [+] feedback
cydmx256a16, cydmx256b16 cydmx128a16, cydmx128b16 cydmx064a16, cydmx064b16 document #: 001-08090 rev. *g page 17 of 25 figure 7. standard port write cycle (right port access, we# controlled) figure 8. standard port write cycle (right port access, cs# controlled) valid address address oe# we# cs# twc tlzwe ub#, lb# t b w data valid data taw tsa twrl tsd thd thzwe tha valid address address oe# we# cs# twc tlzcs ub#, lb# t b w data valid data taw tsa twrl tsd thd thzwe tha tscs [+] feedback
cydmx256a16, cydmx256b16 cydmx128a16, cydmx128b16 cydmx064a16, cydmx064b16 document #: 001-08090 rev. *g page 18 of 25 figure 9. arbitration timing figure 10. arbitration timing (address controlled with left adm and right standard configuration address match address l & r cs#l busy#l cs#r tblc tps tbhc address match address r busy#r tbla left address valid first tps tbha i/ol[15:0] mismatch adv#l address l (internal) tavdh valid left address address r busy#l tbla tps tbha i/ol[15:0] adv#l address l (internal) tavdh data address match tavdh valid address valid address mismatch valid address right address valid first [+] feedback
cydmx256a16, cydmx256b16 cydmx128a16, cydmx128b16 cydmx064a16, cydmx064b16 document #: 001-08090 rev. *g page 19 of 25 figure 11. arbitration timing (address controlled with left adm and right adm configuration) figure 12. read with busy# timing address r (internal) busy#r tbla tps tbha adv#l address l (internal) tavdh tavdh mismatch adv#r tavdh address match address r busy#r i/ol[15:0] avd#l we#l data valid address valid address address match twdd tddd data out r valid data tbdd [+] feedback
cydmx256a16, cydmx256b16 cydmx128a16, cydmx128b16 cydmx064a16, cydmx064b16 document #: 001-08090 rev. *g page 20 of 25 figure 13. interrupt timing cs#l int#r tins thd right mailbox addr i/ol[15:0] oe#l write data we#l cs# or we#, whichever assert low later cs# or we#, whichever assert high first left port writes right mailbox to set int#r right port reads right mailbox to clear int#r right mailbox addr address r oe#r we#r cs#r int#r tinr cs#, oe# or we#, whichever assert latest [+] feedback
cydmx256a16, cydmx256b16 cydmx128a16, cydmx128b16 cydmx064a16, cydmx064b16 document #: 001-08090 rev. *g page 21 of 25 ordering information ordering code definitions table 7. 16 k 16 mobl ad m asynchronous dual-port sram speed (ns) ordering code package name package type operating range 65 cydmx256a16-65bvxi bz100 100-ball pb-free 0.5 mm pitch bga industrial 65 cydmx256b16-65bvxi bz100 100-ball pb-free 0.5 mm pitch bga industrial 90 cydmx256a16-90bvxi bz100 100-ball pb-free 0.5 mm pitch bga industrial table 8. 8 k 16 mobl adm asynchronous dual-port sram speed (ns) ordering code package name package type operating range 65 cydmx128a16-65bvxi bz100 100-ball pb-free 0.5 mm pitch bga industrial 65 cydmx128b16-65bvxi bz100 100-ball pb-free 0.5 mm pitch bga industrial table 9. 4 k 16 mobl adm asynchronous dual-port sram speed (ns) ordering code package name package type operating range 65 cydmx064b16-65bvxi bz100 100-ball pb-free 0.5 mm pitch bga industrial 90 CYDMX064A16-90BVXI bz100 100-ball pb-free 0.5 mm pitch bga industrial temperature range: i = industrial x = pb-free package type: bv = 100-ball bga latency in ns: 65 / 90 bus width version dual-port density in kb: 064 / 128 / 256 x = ad mux interface no x = standard sram interface cydm = cypress mobl dual-port cydm xxx xx - i bv x xx x x [+] feedback
cydmx256a16, cydmx256b16 cydmx128a16, cydmx128b16 cydmx064a16, cydmx064b16 document #: 001-08090 rev. *g page 22 of 25 package diagram figure 14. 100-ball vfbga (6 6 1.0 mm) bz100a 51-85209 *d [+] feedback
cydmx256a16, cydmx256b16 cydmx128a16, cydmx128b16 cydmx064a16, cydmx064b16 document #: 001-08090 rev. *g page 23 of 25 acronyms document conventions units of measure acronym description cs# chip select bga ball grid array cmos complementary metal oxide semiconductor i/o input/output lvcmos low voltage complementary metal oxide semiconductor lvttl low voltage transistor-transistor logic odr output drive register oe# output enable sram static random access memory ttl transistor-transistor logic vfbga very fine-pitch ball grid array we# write enable symbol unit of measure c degree celsius a micro amperes mhz mega hertz ma milli amperes ms milli seconds mm milli meter ns nano seconds ? ohms pf pico farad mv milli volts vvolts wwatts % percent [+] feedback
cydmx256a16, cydmx256b16 cydmx128a16, cydmx128b16 cydmx064a16, cydmx064b16 document #: 001-08090 rev. *g page 24 of 25 document history page document title: cydmx256a16, cydmx128a16, cydm x064a16, cydmx256b16, cydmx128b16, cydmx064b16, 16 k/8 k/4 k 16 mobl ? adm asynchronous dual-port static ram document number: 001-08090 rev. ecn no. orig. of change submission date description of change ** 462234 hkh new data sheet *a 491702 hkh removed none applicable timing tbw revised standard port timing numbers corrected typo *b 500425 hkh updated twc, tscs to reflect bin spec added note for special condition of tps updated dc data that are previously tbd added note for tlzoe that is guaranteed by design by not tested *c 2147866 ydt/hkh /aesa see ecn relaxed -65 standard port timing to match the standard port timing of -90. added new devices cydmx256b16, cydmx128b16 and cydmx064b16. *d 3031102 ved 09/15/2010 changed to post on the external web. no other change. *e 3053582 hkh 10/08/2010 removed pruned device cy dmx064a16-65bvxi from ordering information. updated sales links. added ordering code definition and table of contents. *f 3209987 hkh 03/30/2011 updated ordering information . updated package diagram . updated in new template. *g 3246085 hkh 05/02/2011 added acronyms and units of measure . [+] feedback
document #: 001-08090 rev. *g revised may 2, 2011 page 25 of 25 mobl is a registered trademark of cypress semiconductor corporation. all products and company names mentioned in this document may be the trademarks of their respective holders. cydmx256a16, cydmx256b16 cydmx128a16, cydmx128b16 cydmx064a16, cydmx064b16 ? cypress semiconductor corporation, 2006-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback

▲Up To Search▲

Price & Availability of CYDMX064A16-90BVXI

	To Download CYDMX064A16-90BVXI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .